Author/Creator: Loi, Igor - British Library Electronic Legal Deposit Catalogue-Journal Issues and Articles Search Results

Author/Creator Loi, Igor

1. A 60 GOPS/W, −1.8 V to 0.9 V body bias ULP cluster in 28 nm UTBB FD-SOI technology. (March 2016)

Authors:: Rossi, Davide; Pullini, Antonio; Loi, Igor; Gautschi, Michael; Gürkaynak, Frank K.; Bartolini, Andrea; Flatresse, Philippe; Benini, Luca
Journal:: Solid-state electronics
Issue:: Volume 117(2016)
Page Start:: 170
Record Type:: Journal Article
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2. A 60 GOPS/W, −1.8 V to 0.9 V body bias ULP cluster in 28 nm UTBB FD-SOI technology. (March 2016)

Authors:: Rossi, Davide; Pullini, Antonio; Loi, Igor; Gautschi, Michael; Gürkaynak, Frank K.; Bartolini, Andrea; Flatresse, Philippe; Benini, Luca
Journal:: Solid-state electronics
Issue:: Volume 117(2016)
Page Start:: 170
Record Type:: Journal Article
View Content:: Available online (eLD content is only available in our Reading Rooms) ↗

3. A case for three‐dimensional stacking of tightly coupled data memories over multi‐core clusters using low‐latency interconnects. Issue 5 (1st September 2013)

Authors:: Azarkhish, Erfan; Loi, Igor; Benini, Luca
Journal:: IET computers & digital techniques
Issue:: Volume 7:Issue 5(2013)
Page Start:: 191
Record Type:: Journal Article
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4. Area and Power Modeling for Networks-on-Chip with Layout Awareness. (30th April 2007)

Authors:: Meloni, Paolo; Loi, Igor; Angiolini, Federico; Carta, Salvatore; Barbaro, Massimo; Raffo, Luigi; Benini, Luca
Other Names:: Palesi Maurizio Academic Editor.
Journal:: VLSI design
Issue:: Volume 2007(2007)
Page Start:
Record Type:: Journal Article
View Content:: Available online (eLD content is only available in our Reading Rooms) ↗