1. Architecture optimization of SPAD integrated in 28 nm FD-SOI CMOS technology to reduce the DCR. (May 2022) Authors: Issartel, D.; Gao, S.; Pittet, P.; Cellier, R.; Golanski, D.; Cathelin, A.; Calmon, F. Journal: Solid-state electronics Issue: Volume 191(2022) Page Start: Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗