1. Low voltage logic circuits exploiting gate level dynamic body biasing in 28 nm UTBB FD-SOI. (March 2016) Authors: Taco, Ramiro; Levi, Itamar; Lanuzza, Marco; Fish, Alexander Journal: Solid-state electronics Issue: Volume 117(2016) Page Start: 185 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗
2. Low voltage logic circuits exploiting gate level dynamic body biasing in 28 nm UTBB FD-SOI. (March 2016) Authors: Taco, Ramiro; Levi, Itamar; Lanuzza, Marco; Fish, Alexander Journal: Solid-state electronics Issue: Volume 117(2016) Page Start: 185 Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗