1. Through-silicon-via induced stress-aware FinFET buffer sizing in 3D ICs. (1st August 2022) Authors: Yadav, Sarita; Chauhan, Nitanshu; Chawla, Raghav; Sharma, Arvind; Banchhor, Shashank; Pratap, Rajendra; Anand, Bulusu Journal: Semiconductor science and technology Issue: Volume 37:Number 8(2022) Page Start: Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗