Author/Creator: Cellier, R. - British Library Electronic Legal Deposit Catalogue-Journal Issues and Articles Search Results

Author/Creator Cellier, R.

1. Architecture optimization of SPAD integrated in 28 nm FD-SOI CMOS technology to reduce the DCR. (May 2022)

Authors:: Issartel, D.; Gao, S.; Pittet, P.; Cellier, R.; Golanski, D.; Cathelin, A.; Calmon, F.
Journal:: Solid-state electronics
Issue:: Volume 191(2022)
Page Start:
Record Type:: Journal Article
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2. Design guidelines for the integration of Geiger-mode avalanche diodes in standard CMOS technologies. Issue 10 (October 2015)

Authors:: Vignetti, M.M.; Calmon, F.; Cellier, R.; Pittet, P.; Quiquerez, L.; Savoy-Navarro, A.
Journal:: Microelectronics journal
Issue:: Volume 46:Issue 10(2015)
Page Start:: 900
Record Type:: Journal Article
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3. Preliminary simulation study of a coincidence Avalanche Pixel Sensor. (12th June 2015)

Authors:: Vignetti, M.M.; Calmon, F.; Cellier, R.; Pittet, P.; Quiquerez, L.; Savoy-Navarro, A.
Journal:: Journal of instrumentation
Issue:: Volume 10:Number 6(2015:Jun.)
Page Start:: C06007
Record Type:: Journal Article
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