1. Area and Power Modeling for Networks-on-Chip with Layout Awareness. (30th April 2007) Authors: Meloni, Paolo; Loi, Igor; Angiolini, Federico; Carta, Salvatore; Barbaro, Massimo; Raffo, Luigi; Benini, Luca Other Names: Palesi Maurizio Academic Editor. Journal: VLSI design Issue: Volume 2007(2007) Page Start: Record Type: Journal Article View Content: Available online (eLD content is only available in our Reading Rooms) ↗